Out-of-order execution of instructions within a processor occurs for certain compute intensive tasks like signal processing. However, in-order execution of memory mapped input/output (MMIO) accesses is required to guarantee correct execution in embedded control applications. To effect such operation, a programmer introduces special (e.g., fence/barrier) instructions to ensure in-order execution. However, this technique is error prone, and makes high-level code less portable across instruction set architectures, less readable, and less re-useable.
Historically, embedded systems such as small control units included in industrial, automotive and other specialized environments were architected with an in-order processor architecture. As more compute complex activities are performed in embedded applications, out-of-order processing architectures are being introduced, which increases complexity and suffers from backwards compatibility issues with existing code bases.